Understanding level of Abstraction in Verilog HDL

Data Abstraction

Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction level, the module would behave exactly in the similar way to the external environment. Following are the four different levels of abstraction which can be described by four different coding styles of Verilog language:

1. Switch level
2. Gate level
3. Data flow level
4. Behavioral level

The order of abstraction mentioned above are from Lowest to Highest level of abstraction.In this post you will see all the level with there Verilog code examples.

Switch Level :-

It was the first or we can say the basic level of abstraction that was used by designers for chip designing purposes. It provided the transistor or MOS level modelling to the designers. This level is now rarely used due to complexity of chip design designers had moved to higher level of abstraction.

lets take a example having a control signal(cs) , input(in) and output(os). Now a switch level Verilog code would be

Module Block (osn osp ,in,cs);

output osn,osp; //output for pmos and nmos

input in,cs;

nmos(osn,in,cs);

pmos(osp,in,cs);

endmodule

Gate Level :-

It was the second and higher level of abstraction than Switch level that was used by designers for chip designing purposes. It provided the Logic gate rather than transistor or MOS for modelling . This level is now rarely used due to complexity of chip design designers had moved to higher level of abstraction.

Modeling done at this level is called gate-level modeling as it involves gates and has a one to one relationship between a hardware schematic and the Verilog code.The multiple-input gates are and, nand, or, nor, xor, and xnor whose number of inputs are two or more, and has only one output

Lets us consider a example for half_adder to understand the code of this level . Here we take the Input as in0,in1 and output of half adder as sum and carry. so this will the following verilog code for this section.

module half_adder (sum, carry, in0, in1);

output sum, carry;

input in0, in1;

xor xor_1 (sum, in0, in1);

and and_1 (carry, in0, in1);

endmodule

Data flow Level:-

It is Higher level of abstraction than Gate level that was used by designers for chip designing purposes. It provided the operator , delays , assignments rather than transistor or MOS for modelling . This level is currently in use for f chip designing purposes .

Dataflow modeling makes use of the functions that define the working of the circuit instead of its gate structure. Dataflow modeling has become a popular design approach, as logic synthesis tools became sophisticated. This approach allows the designer to focus on optimizing the circuit in terms of the flow of data.

Lets again take the example of a half adder and learn how this level of codinf is done in verilog. Here we have used assign statements for assignment of data and &,^ operator of And and Xor operation respectively.

module halfadder(a,b,sum,carry);

input a,b;

output sum,carry;

assign sum=a ^ b ;

assign carry=a & b;

endmodule

Behavioral level:-

This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details.It specifies the circuit in terms of its expected behavior.It is the closest to a natural language description of the circuit functionality, but also the most difficult to synthesize. We can use different loop , if else statements , case equality Task and functions and many more. so it is called as the best approach of abstraction in HDL now a days.

Lets consider the block example of full adder and understand the code.Here we have used always statement which is like a loop statement and taken out output as a register type. @ here is considered as the delay operator and () are called as sensitivity list.

module full_adder ( a,b,cin,sum,cout);

input wire a,b,cin;

output reg s,cout;

always @(a or b or cin)

begin

s≤a^b^cin;

cout≤ a&b|(a^b)&cin;

end

endmodule

That was all about the level of abstraction used in Verilog.

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