UART Transmitter
My previous post was about Baud Rate Generator. Today’s post will mainly focus on the 2nd module used i.e. UART Transmitter and its Hardware description language (HDL) code.
UART transmitter is used here to transmit the serial data to receiver module of other UART device . We input the data in parallel form but it is sended out serially. It means our input data goes through certain operations making it compatible for transmission. Transmitter module converts the parallel data into serial bit stream.
This module is further divided into 4 sub modules:
1.Tx Controllerfsm
- Generates all the necessary signal required to transmit data at right time. Act as the brain of transmitter.
2.Parity generator
- Generate parity for the 8bit input data. It is calculated by xoring the input data.
3. PISO(Parallel In Serial Out)
- Takes the 8bit input binary data and convert it into serial data for transmission.
4.TxMux(Transmitter multiplexer)- It is a 4:1 Multiplexer to transmit 4 different type of data viz. start bit, data bit, parity bit and the stop bit. these all together with input data make a single data packet.
Verilog code:-
TX FSM:-
module tx_fsm(shift, load,sel,reset,clk,txstart);
input txstart,clk,reset;
output reg load,shift;
output reg [1:0]sel;
reg temp,temp1;
reg [2:0]state=3'b000;
reg [2:0]nextstate=3'b000;
reg x,flag2;
reg [3:0]count=4'd0;
reg [2:0]flag=0;
parameter idle=3'b000,startbit=3'b001,databit=3'b010,paritybit=3'b011,stopbit=3'b100;
always@(*)
begin
case(state)
idle:begin nextstate=txstart?startbit:idle; load=0; shift=0;sel=2'b11;temp=0;temp1=0;end
startbit:begin nextstate=flag2?databit:startbit; load=1; shift=0; sel=2'b00;temp=1;temp1=0;end
databit:begin nextstate=x?paritybit:databit; load=0; shift=1; sel=2'b01; temp=0;temp1=1;end
paritybit:begin nextstate=flag2?stopbit:paritybit; load=0; shift=0; sel=2'b10; temp=1;temp1=0;end
stopbit:begin nextstate=flag2?idle:stopbit ; load=0; shift=0; sel=2'b11;temp=1;temp1=0;end
default:begin nextstate=idle; load=0; shift=0;sel=2'b11;temp=0;temp1=0; end
endcase
end
always@(posedge clk)
begin
if(temp1)
begin
if(flag==3'd7)
begin
flag=0;
x=1;
end
else
begin
x=0;
flag=flag+1;
end
end
else
begin
flag=0;
x=0;
end
end
always@(posedge clk)
begin
if(count==15)
begin
flag2=1;
count=0;
end
else
begin
flag2=0;
count=count+1;
end
end
always@(posedge clk,negedge reset)
begin
if(~reset)
state<=idle;
else
state<=nextstate;
end
endmodule
PISO:-
module piso(databit,
txdata,
load,
shift,
clk,
reset);
input load,shift,clk,reset;
input [7:0] txdata;
output reg databit=0;
reg[7:0]temp=7'd0;
always @ (posedge clk, negedge reset)
begin
if (!reset)
begin
databit<=1'b0;
end
else if (load)
temp<=txdata;
else
begin
databit<=temp[0];
temp<=temp>>1'b1;
end
end
endmodule
Parity generator:-
module parity_generator(paritybit,txdata,load);
output reg paritybit;
input [7:0]txdata;
input load;
always@(*)
begin
if (load)
paritybit<=^txdata;
else
paritybit<=1'b0;
end
endmodule
TxMux:-
module TXmux (TXdataout,Databit,Paritybit,sel);
output reg TXdataout;
input Databit,Paritybit;
input [1:0]sel;
always@(*)
begin
case(sel)
2'b00: TXdataout=0;
2'b01: TXdataout=Databit;
2'b10: TXdataout=Paritybit;
2'b11: TXdataout=1;
default TXdataout=0;
endcase
end
endmodule
RTL Design for Transmitter module:-
This is the front end design for the module one can test this module by writing the test bench and checking its behavior for different inputs.
Tool used:- Xiline design suite and Isim simulator
Hope you find this post informative . Keep an eye for my next post which will be on Verilog coding and detailed explanation of last module i.e. UART Receiver .
Thanks for reading.