UART RECEIVER

3 min readJan 6, 2021

Today’s post will focus on the last module used i.e. UART Receiver and its Hardware description language (HDL) code.

UART Receiver is used here to receive the serial data from transmitter module of other UART device . We receive the data in serial form but it is sended out in parallel form. As its difficult for us to understand the serial data. Receiver module converts the serial data into parallel bit stream.

This module is further divided into 5 sub modules:

1.Rx_fsm

- Generates all the control signal for UART receiver.

2. Detect Start

- Ideally the receiver receives continuous 1, as soon as the 0 is detected which is done by this module, the reception of data starts.

3. SIPO (Serial IN Parallel Out)

- Converts serial data into 8 bit parallel data.

4. Parity Checker

- checks the correctness of data by Xoring the 10th received bit with xor value of 8 bit received data

5. Stop bit Checker

- After the detection of valid parity bit, the stop bit is detected, if the stop bit is not detected then reception of data is terminated by setting stop bit error signal high.

Verilog code:-

Detect Start:-

module detect_bit( startbit,rxin,clk);
input rxin,clk;
output reg startbit;
reg [3:0]x=0;
always@(posedge clk)
begin
if(!rxin)
begin
if (x==4'd12)
begin
startbit=1;
x=0;
end
else
begin
startbit=0;
x=x+1;
end
end
else
begin
x=0;
startbit=0;
end
end
endmodule

SIPO:-

module sipo_(dout,clk,shift,reset,Rxin);
input clk,reset,shift;
input Rxin;
output [7:0]dout;
reg [7:0]s=0;always @(posedge clk,negedge reset )
begin
if (!reset)
begin
s=0;
end
else if(shift)
begin
s=s>>1;
s[7]=Rxin;
end
else
s=s;
end
assign dout=s;
endmodule

Parity checker:-

module parity_checker(paritybiterror,load,dout,dout1,rxin,reset);
input load,rxin,reset;
input [7:0]dout;
reg[7:0]a;
wire [7:0]b;
output reg paritybiterror;
output [7:0]dout1;
assign b=dout;
always@(*)
begin
if (!reset)
a<=8'h00;
else if (load)
begin
if (rxin==(^b))
begin
a<=dout;
paritybiterror<=0;
end
else
begin
paritybiterror<=1;
a<=a;
end
end
else
begin
paritybiterror<=0;
a<=a;
end
end

assign dout1=a;
endmodule

Stop Bit error:-

module stop_bit (dout1,rxdataout,stopbiterror,rxin,checkstop,clk,reset);
input rxin,checkstop,clk,reset;
input [7:0]dout1;
output reg stopbiterror;
output reg [7:0] rxdataout =0;
reg x=3'd0;

always@(posedge clk)
begin
if (checkstop)
begin
if(rxin)
begin
if(x==15)
begin
x<=0;
rxdataout<=dout1;
stopbiterror<=0;
end
else
begin
x=x+1;
stopbiterror<=0;
rxdataout<=dout1;
end
end
else
begin
rxdataout<=8'd0;
stopbiterror<=1;
end
end
else
begin
rxdataout<=dout1;
stopbiterror<=0;
end

end
endmodule

RX FSM:-

module fsm_reciver(shift,
load,
checkstop,
startbit,
paritybiterror,
clk,
reset);

input startbit,clk,reset,paritybiterror;
output reg load,shift,checkstop;
parameter idle=2'b00,data=2'b01,paritybit=2'b10,stopbit=2'b11;
reg [1:0]state=2'b00;
reg [1:0]nextstate=2'b00;
reg flag2=0;
reg flag=0;
reg temp=0;
reg temp1=0;
reg [3:0]x=4'd0;
reg[3:0]count=4'd0;
always@(*)
begin
case(state)

idle:begin nextstate=startbit?data:idle; load=0; shift=0;temp=0;temp1=0;end
data:begin nextstate=flag?paritybit:data; load=0; shift=1;temp=1;temp1=0;end
paritybit:begin nextstate=flag2?idle:(flag?stopbit:paritybit);temp=0;temp1=1; load=1; shift=0; end

stopbit:begin nextstate=flag2?idle:stopbit; load=0; shift=0; checkstop=1;temp=0;temp1=1;end
endcase
end

always@(posedge clk)
begin
if(temp)
begin
if(x==3'd7)
begin
x<=3'd0;
flag<=1;
end
else
begin
flag<=0;
x<=x+1;
end
end
else
begin
flag<=0;
x<=0;
end
end

always@(posedge clk)
begin
if(temp1)
begin
if(count==15)
begin
flag2=1;
count=0;
end
else
begin
flag2=0;
count=count+1;
end
end
else
begin
count=0;
flag2=0;
end
end
always@(posedge clk,negedge reset)
begin
if(~reset)
state<=idle;
else
state<=nextstate;