INTRA/INTER Assignment in Verilog

This is a term all the students who have for appeared in an Interview in a VLSI Based company should be familiar with it . It is one of the most favorite questions from almost every interviewer.

These terms are basically associated with the assignment of data bit to a register during simulation or Runtime.This you will get to know with explained example of it.

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INTRA ASSIGNMENT:-

Look at the following piece of code. We have defined register X,Y,Z and applied a delay using the (#) delay operator in the initial begin end statements.

//define register variables
reg x,y,z
initial
begin
x = 0; z= 0; //This delay is all about at what time the value are taken and what time they are assigned to the register.
y = #5 x+ z; //It take value of x and z at the simulation time=0, evaluate x + z and then wait 5 time units to assign value to y.
end

These assignment statement is generally used in Blocking statements for making Combinational Logic for example MUX, Encoder , Decoder etc.

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INTER ASSIGNMENT:-

Again lets take the same example but now with little changes in variables.We will be using an additional temporary variable for the explanation.

//define register variables
reg x,y,z

//Temporary variables
initial
begin
x = 0; y= 0;
temp = x+ z;
#5 y= temp; //Take value of x+ z at the current time and store it in a temporary variable. Even though y and z might change between 0 and 5, the value assigned to y at time 5 is unaffected.
end

These assignment statement is generally used in Non Blocking statements for making Sequential Logic for example Flip flop, counters etc

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