Rohit ThakurinNerd For TechAre you preparing for a VLSI-based Industry?Hola Peeps,3 min read·May 31, 2021----
Rohit ThakurUnderstanding level of Abstraction in Verilog HDLVerilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each…3 min read·Jan 24, 2021----
Rohit ThakurINTRA/INTER Assignment in VerilogThis is the term all the students who appeared for a VLSI based interview had gone through with. It is one of the favorite question for…2 min read·Jan 17, 2021----
Rohit ThakurUART RECEIVERToday’s post will focus on the last module used i.e. UART Receiver and its Hardware description language (HDL) code.3 min read·Jan 6, 2021--2--2
Rohit ThakurUART TransmitterMy previous post was about Baud Rate Generator. Today’s post will mainly focus on the 2nd module used i.e. UART Transmitter and its…3 min read·Jan 2, 2021----
Rohit ThakurBaud Rate Generator (UART)My previous post was about UART Protocol overview and its working. Today’s post will mainly focus for its internal structure and How one…2 min read·Jan 1, 2021--1--1
Rohit ThakurUniversal Asynchronous Receiver Transmitter (UART)Is a popular and most widely used Protocol for Serial data communication. It is used for transmitting and receiving data asynchronously…4 min read·Dec 31, 2020----
