Published inNerd For TechAre you preparing for a VLSI-based Industry?Hola Peeps,May 31, 2021May 31, 2021
Understanding level of Abstraction in Verilog HDLVerilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each…Jan 24, 2021Jan 24, 2021
INTRA/INTER Assignment in VerilogThis is the term all the students who appeared for a VLSI based interview had gone through with. It is one of the favorite question for…Jan 17, 2021Jan 17, 2021
UART RECEIVERToday’s post will focus on the last module used i.e. UART Receiver and its Hardware description language (HDL) code.Jan 6, 20212Jan 6, 20212
UART TransmitterMy previous post was about Baud Rate Generator. Today’s post will mainly focus on the 2nd module used i.e. UART Transmitter and its…Jan 2, 2021Jan 2, 2021
Baud Rate Generator (UART)My previous post was about UART Protocol overview and its working. Today’s post will mainly focus for its internal structure and How one…Jan 1, 20211Jan 1, 20211
Universal Asynchronous Receiver Transmitter (UART)Is a popular and most widely used Protocol for Serial data communication. It is used for transmitting and receiving data asynchronously…Dec 31, 2020Dec 31, 2020
